FPGA (VHDL, Verilog) Development Process (HiREL)

ProtectedLogic supports our customers by giving them the capability of describing their design requirements in various ways. We work with our customer to construct an FPGA requirements specification to outline the interfaces and internal functionality before we begin designing.

Our basic FPGA requirements segmentation process generates a baseline Design Document
1) The designer segments the design into unique functional blocks
2) The requirements are allocated to the functional blocks
3) The functional block requirements are used to define interface/data needs
4) The interfaces are allocated to the functional blocks
5) Requirements are defined /documented for the individual functional blocks with port definitions
6) Requirements are defined for the test bench (TB) of the FPGA
7) Document above design details in a Design Document
8) Create or Expand the validation matrix to include the requirements, test method and test results
9) VHDL or Verilog code implementation starts
Our Basic Code Implementation Process for Custom Designs
1) Construct the entity with Interfaces for the highest FPGA level
2) Construct the TB to stimulate and test the external interfaces
3) Develop the lower level entities within the FPGA
4) Increase the capabilities of the TB as the design matures
5) Develop Test Scripts to check against the validation matrix
6) Run regression testing on the design
7) Review all data with the customer (Design Review)
8) Deliver
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HDL Coding Approach to High Reliability